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The complete portfolio includes the ARC EM22FS, HS4xFS, EV7xFS, and VPX5FS safety processors with integrated hardware-safety features to detect system errors.
ARC SYNOPSYS ISO
The ARC Functional Safety processors support ASIL B and ASIL D safety levels to simplify safety-critical automotive system on chip (SoC) development and accelerate ISO 26262 qualification.
ARC SYNOPSYS SOFTWARE
“We are pleased to be the first automotive software company to collaborate with Synopsys on a software solution for its ARC Functional Safety processors, providing a turnkey approach that makes it quicker and easier for customers to develop automotive safety applications.” “Elektrobit has been active in the development of the AUTOSAR standard from its inception and continues to be a leader in AUTOSAR software and tools,” said Artur Seidel, Vice President for Americas at Elektrobit. The combined solution accelerates time to market for the complex automotive electronic control units (ECUs) required for application such as ADAS, infotainment and gateways, and vehicle-to-everything (V2X) systems used in modern vehicles. This version of the EB tresos AUTOSAR software used with the ARC Functional Safety processors provides a hardware-software platform that makes it easier for automotive semiconductor companies, OEMs, and Tier 1 suppliers to develop software applications based on the AUTOSAR standard. (Nasdaq: SNPS) and Elektrobit, a visionary global supplier of embedded and connected software products for the automotive industry, today announced availability of EB tresos Classic AUTOSAR software for Synopsys’ ASIL-D compliant DesignWare® ARC® EM and ARC HS Functional Safety (FS) Processor IP. Half-precision (FP16) support is a new feature along with single-precision (FP32), the HS6x handles double precision (FP64) as well.MOUNTAIN VIEW, Calif., and ERLANGEN, Germany, – Synopsys, Inc. The scalar FPU operates with a dedicated register file.
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Designers can also include a trace block that works with CoreSight and Nexus debug, as well as a cluster DMA, FPU, and MPU. FastMath increases performance for a subset of math operations that DSPs often employ, such as exponential, logarithm, square root, and trig functions. The new high-speed interconnect can deliver up to 800GB/s of intracluster bandwidth, and according to the company’s calculations, it reduces by 80% the number of wires between cores and the rest of the cluster, increasing area efficiency.Īll of the new HS cores support the optional FastMath pack, which plugs into the instruction space reserved for the ARC Processor Extension (Apex). But in response to customer demand for higher-performance embedded processors, the company developed a new interconnect that raises the limit to 12 cores-more than any other licensable CPU. Previous-generation ARC CPUs can serve in dual- and quad-core cache-coherent clusters. Production RTL is scheduled for general licensing in 3Q20. The HS6x and HS5x target solid-state drives (SSDs), networking equipment, wireless infrastructure, and other high-performance embedded systems. ARCv3-based cores are software compatible with previous-generation ARC cores, but they add instructions that the new 32-bit HS5x family supports as well. Synopsys has developed its first 64-bit ARC CPU cores, called the HS6x family, implementing its new ARCv3 ISA.